1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to techniques for the formation of conductive interconnects.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the size, or scale, of the components of a typical transistor also requires reducing the size and cross-sectional dimensions of electrical interconnects to contacts to active areas, such as N+ (P+) source/drain regions and a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor, and the like. As the size and cross-sectional dimensions of electrical interconnects get smaller, resistance increases and electromigration increases. Aluminum (Al) is most often used for interconnects in contemporary semiconductor fabrication processes primarily because aluminum is inexpensive and easier to etch than, for example, copper (Cu). However, aluminum has poor electromigration characteristics and higher resistivity than other metals, including copper.
As a result of the difficulty in etching copper, when it is used, an alternative approach to forming vias and metal lines is typically employed. The damascene approach, consisting of etching openings such as trenches in the dielectric for lines and vias and creating in-laid metal patterns, is the leading contender for fabrication of sub-0.25 micron (sub-0.25μ) design rule copper-metallized (Cu-metallized) circuits.
In the damascene approach, vias, contact openings and trenches, for example, may be formed in and through dielectric layers and other process layers using known photolithography techniques. A layer or film of copper is then formed over the surface of the dielectric, filling the openings and trenches. The excess copper is then removed by polishing, grinding, and/or etching, such as by chemical/mechanical polishing, to leave only the copper in the openings or trenches, which form the copper interconnects.
Additionally, as semiconductor device geometry continues to shrink, providing insulating material between conductive layers or interconnects becomes more problematic. Improved dielectric materials having low dielectric constants, for example, 4.0 and lower, have been developed. By using these “low k” materials, dielectric layers may be formed somewhat thinner while maintaining the needed insulative characteristics. However, these low k dielectric films may be damaged by etching and ashing processes associated with the use of photoresist masks, for example. Damage to these low k dielectric films due to photoresist ash processes can lead to increased line-to-line capacitance, leakage, poor interface adhesion with barrier metals and passivation layers, and decreased reliability. Further, these low k dielectric films contain nitrogen impurities that can cause DUV photoresist poisoning if the photoresist is in direct contact with the low k material.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.